TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

Description The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock

2-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectabl 2- 0.7 V HCSL differential output pairs\nPhase jitter: PCIe Gen3 < 1 ps rms\nPhase jitter: PCIe Gen2 < 3.1 ps rms\nPhase jitter: PCIe Gen1 < 86 ps peak to peak\nSupports zero delay buffer mode and fanout mode\nBandwidth programming available\n33-110 MHz operation in PLL mode\n10-110 MHz operation in;

SMBus Interface; allows control of PLL BW and Mode

文件：211.55 Kbytes Page：17 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

封装/外壳：20-SSOP（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK FANOUT/BUFF ZD 20QSOP 集成电路（IC） 应用特定时钟/定时

封装/外壳：20-SSOP（0.154"，3.90mm 宽） 包装：托盘 描述：IC CLK FANOUT/BUFF ZD 20QSOP 集成电路（IC） 应用特定时钟/定时

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages

Two Output Differential Buffer for PCIe Gen3

文件：198.58 Kbytes Page：14 Pages