Nineteen Output Differential Buffer for PCIe Gen3

General Description The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the in

19-output Differential Buffer For PCIe Gen3

The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selecta • 19 - 0.7 V current mode differential HCSL output pairs\n• 11 dedicated and 3 group OE# pins/Hardware control of the outputs\n• Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's\n• SMBus Interface, unused outputs can be disabled\n• Cycle-to-cycle jitter <50 ps\n• PCIe Gen3 phase;

Nineteen Output Differential Buffer for PCIe Gen3

文件：186.37 Kbytes Page：17 Pages

Nineteen Output Differential Buffer for PCIe Gen3

文件：186.37 Kbytes Page：17 Pages

封装/外壳：72-VFQFN 裸露焊盘 包装：托盘 描述：IC CLK FANOUT/BUFF ZD 72VFQFN 集成电路（IC） 应用特定时钟/定时

Nineteen Output Differential Buffer for PCIe Gen3

文件：186.37 Kbytes Page：17 Pages

封装/外壳：72-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC CLK FANOUT/BUFF ZD 72VFQFN 集成电路（IC） 应用特定时钟/定时