12-Output Differential Buffer for PCIe Gen3

Description The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input cloc

12-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selecta 12 - 0.7 V current mode differential HCSL output pairs\n3 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment\n12 OE# pins/Hardware control of each output\nPLL or bypass mode/PLL can dejitter incoming clock\nSelectable PLL bandwidth/minimizes jitter peaking in downstream PLL;

Twelve Output Differential Buffer for PCIe Gen3

文件：187 Kbytes Page：15 Pages

SMBus Interface/unused outputs can be disabled

文件：187 Kbytes Page：15 Pages

Twelve Output Differential Buffer for PCIe Gen3

文件：187 Kbytes Page：15 Pages

封装/外壳：64-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC CLK FANOUT/BUFF ZD 64TSSOP 集成电路（IC） 应用特定时钟/定时

Twelve Output Differential Buffer for PCIe Gen3

文件：187 Kbytes Page：15 Pages

封装/外壳：64-TFSOP（0.240"，6.10mm 宽） 包装：卷带（TR） 描述：IC CLK FANOUT/BUFF ZD 64TSSOP 集成电路（IC） 应用特定时钟/定时