Six Output Differential Buffer for PCIe Gen 2

Description The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize per

6-output Differential Buffer For PCIe Gen2

The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems 6 - 0.7 V current mode differential output pairs (HCSL)\nCLKREQ# pin for outputs 1 and 4/ supports Express Card applications\nPLL or bypass mode/PLL can dejitter incoming clock\nSelectable PLL bandwidth/minimizes jitter peaking in downstream PLL's\nSpread Spectrum Compatible/tracks spreading input c;

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC BUFFER 6OUTPUT PCI 28-SSOP 集成电路（IC） 应用特定时钟/定时

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC BUFFER ZD 6OUTPUT 28-SSOP 集成电路（IC） 应用特定时钟/定时

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

Six Output Differential Buffer for PCIe Gen 2

文件：193.55 Kbytes Page：14 Pages

6 Output PCI Express Buffer with CLKREQ Function

文件：118.53 Kbytes Page：9 Pages

6 Output PCI Express Buffer with CLKREQ Function

文件：118.53 Kbytes Page：9 Pages