Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

Two Output Differential Buffer for PCIe Gen1 & Gen2

文件：187.59 Kbytes Page：13 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC CLK FANOUT/BUFF ZD 20TSSOP 集成电路（IC） 应用特定时钟/定时

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：IC CLK FANOUT/BUFF ZD 20TSSOP 集成电路（IC） 应用特定时钟/定时

Two Output Differential Buffer for PCIe Gen1 & Gen2

文件：187.59 Kbytes Page：13 Pages

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description Output Features The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maxim

Two Output Differential Buffer for PCIe Gen1 & Gen2

文件：187.59 Kbytes Page：13 Pages

Two Output Differential Buffer for PCIe Gen1 & Gen2

文件：187.59 Kbytes Page：13 Pages

Two Output Differential Buffer for PCIe Gen1 & Gen2

文件：187.59 Kbytes Page：13 Pages