Programmable Timing Control Hub™ for Next Gen P4™ processor

IDT952906A is a 48 pin clock chip for VIA VN800/CN700/P4M800 style chipsets. When used with a fanout DDR buffer, such as the 93788, it provides all the necessary clock signals for such a system. The IDT952906A is part of a whole new line of IDT clock generators and buffers called TCH™ (Timing Contro 3 - 0.7V current-mode differential CPU pairs\n10 - PCI, 3 free running, 33MHz\n2 - REF, 14.318MHz\n3 - 3V66, 66.66MHz\n1 - 48MHz\n1 - 24/48MHz\n2 - 25MHz @ 2.5V;

Programmable Timing Control Hub™ For Next GEN P4™ Processor

Programmable Timing Control Hub™ for Next Gen P4™ processor 3 - 0.7V current-mode differential CPU pairs\n10 - PCI, 3 free running, 33MHz\n2 - REF, 14.318MHz\n3 - 3V66, 66.66MHz\n1 - 48MHz\n1 - 24/48MHz\n2 - 25MHz @ 2.5V\nCPU/SRC outputs cycle-cycle jitter < 125ps\n3V66 outputs cycle-cycle jitter < 250ps\nPCI outputs cycle-cycle jitter < 250ps\nCPU - AGP ske;

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC TIMING CTRL HUB P4 48-TSSOP 集成电路（IC） 应用特定时钟/定时

封装/外壳：48-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC TIMING CTRL HUB P4 48-TSSOP 集成电路（IC） 应用特定时钟/定时

Programmable Timing Control Hub™ for Next Gen P4™ processor

Output Features: • 3 - 0.7V current-mode differential CPU pairs • 10 - PCI, 3 free running, 33MHz • 2 - REF, 14.318MHz • 3 - 3V66, 66.66MHz • 1 - 48MHz • 1 - 24/48MHz • 2 - 25MHz @ 2.5V Key Specifications: • CPU/SRC outputs cycle-cycle jitter

Programmable Timing Control Hub™ for Next Gen P4™ processor

Output Features: • 3 - 0.7V current-mode differential CPU pairs • 10 - PCI, 3 free running, 33MHz • 2 - REF, 14.318MHz • 3 - 3V66, 66.66MHz • 1 - 48MHz • 1 - 24/48MHz • 2 - 25MHz @ 2.5V Key Specifications: • CPU/SRC outputs cycle-cycle jitter

Programmable Timing Control Hub for Next Gen P4??processor

文件：301.56 Kbytes Page：23 Pages

Programmable Timing Control Hub for Next Gen P4??processor

文件：301.56 Kbytes Page：23 Pages

Programmable Timing Control Hub for Next Gen P4??processor

文件：301.56 Kbytes Page：23 Pages