封装/外壳：28-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUF DDR 233MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

封装/外壳：28-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUF DDR 233MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

DDR Phase Lock Loop Clock Driver

Recommended Application: DDR Clock Driver • Low skew, low jitter PLL clock driver • External feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • With bypass mode mux • Operating frequency 60 to 170 MHz • Operating Temperature –45°C to +85°C • CYCLE - CYCL

DDR Phase Lock Loop Clock Driver

Recommended Application: DDR Clock Driver • Low skew, low jitter PLL clock driver • External feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • With bypass mode mux • Operating frequency 60 to 170 MHz • Operating Temperature –45°C to +85°C • CYCLE - CYCL

DDR Phase Lock Loop Clock Driver

文件：66.87 Kbytes Page：9 Pages

Spread Spectrum tolerant inputs

文件：78.04 Kbytes Page：9 Pages