封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER ZD PLL 16TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

High Performance Communication Buffer

Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications. • Less than 125 ps cycle to cycle Jitter • Skew controlled outputs • Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm TSS

High performance Communication Buffer

General Description The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating

High performance Communication Buffer

General Description The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating

High performance Communication Buffer

General Description The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating

High performance Communication Buffer

General Description The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating