丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

丝印代码：90LV018ATM；DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

1FEATURES 2• >400 Mbps (200 MHz) Switching Rates • 50 ps Differential Skew (Typical) • 2.5 ns Maximum Propagation Delay • 3.3V Power Supply Design • Flow-Through Pinout • Power Down High Impedance on LVDS Inputs • Low Power Design (18mW @ 3.3V Static) • Interoperable with Existing 5V LVDS

3V LVDS High-Speed Differential Line Drivers

Description The PI90LV031A, PI90LV027A, and PI90LV017A are differential line drivers that use low-voltage differential signaling (LVDS) to support data rates in excess of 400 Mbps. These products are designed for applications requiring high-speed, low-power consumption and low noise generation.

3V LVDS Single CMOS Differential Line Receiver

文件：241.9 Kbytes Page：10 Pages

3V LVDS Single CMOS Differential Line Receiver

文件：684.69 Kbytes Page：9 Pages

3V LVDS Single CMOS Differential Line Receiver

文件：241.9 Kbytes Page：10 Pages

3V LVDS Single CMOS Differential Line Receiver

文件：684.69 Kbytes Page：9 Pages