Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

General Description The 879893 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two LVCMOS/LVTTL clock signals from which it generates 12 new LVCMOS/LVTTL clock outputs. External PLL feedback is used to also provide zero delay buffer performance

Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

文件：205.2 Kbytes Page：16 Pages

Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

1:12 LVCMOS Dynamic Clock Switch/Generator

The 879893I is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two LVCMOS/LVTTL clock signals from which it generates 12 new LVCMOS/LVTTL clock outputs. External PLL feedback is used to also provide zero delay buffer performance. The 879893I Intelligent Twelve LVCMOS/LVTTL outputs (two banks of six outputs)\nOne QFB feedback clock output\nSelectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs\nCLK0, CLK1 supports the following input types:\nLVCMOS, LVTTL\nAutomatically detects clock failure\nIDCS on-chip intelligent dynamic clock switch\nMaximum output ;

Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

文件：205.2 Kbytes Page：16 Pages

封装/外壳：48-LQFP 包装：卷带（TR） 描述：IC CLK GEN LVCMOS/LVTTL 48-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

文件：205.2 Kbytes Page：16 Pages

封装/外壳：48-LQFP 包装：卷带（TR） 描述：IC CLK GEN LVCMOS/LVTTL 48-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器