Low Skew, 1-to-12 LVCMOS / LVTTL Clock Multiplier/Zero Delay Buffer

FEATURES • Fully integrated PLL • Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential

封装/外壳：52-LQFP 包装：卷带（TR） 描述：IC CLK MULT/ZD BUFFER 52-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer

文件：264.19 Kbytes Page：17 Pages

Low Skew, 1-to-12 LVCMOS / LVTTL Clock Multiplier/Zero Delay Buffer

FEATURES • Fully integrated PLL • Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential

Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer

文件：264.19 Kbytes Page：17 Pages

Low Skew, 1-to-12 LVCMOS / LVTTL Clock Multiplier/Zero Delay Buffer

FEATURES • Fully integrated PLL • Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential

Low Skew, 1-to-12 LVCMOS / LVTTL Clock Mult iplier/Zero Delay Buffer

文件：264.19 Kbytes Page：17 Pages