Low Skew Differential-to-3.3V LVPECL Clock Generator

GENERAL DESCRIPTION The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input level

Low Skew, ÷1/÷2 Differential-to-3.3V LVPECL Clock Generator

FEATURES • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports th

Low Skew,÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator

The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable isin • 2 divide by 1 differential 3.3V LVPECL outputs\n• Selectable differential CLK, nCLK or LVPECL clock inputs\n• PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL\n• Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input\n• Part;

LOW SKEW 첨1/첨2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR

GENERAL DESCRIPTION The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard