÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK GEN 3.3V LVPECL 8-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Differential-to-3.3V LVPECL Clock Generator

文件：198.44 Kbytes Page：15 Pages

÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

Differential-to-3.3V LVPECL Clock Generator

文件：198.44 Kbytes Page：15 Pages

÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

Differential-to-3.3V LVPECL Clock Generator

文件：198.44 Kbytes Page：15 Pages