Low Skew, 1-to-4, Differential-to-HSTL Fantout Buffer

Features • Four differential HSTL compatible outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, C

包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLOCK MANANGEMENT 集成电路（IC） 时钟缓冲器，驱动器

T1/E1 Interface Modules

文件：176.78 Kbytes Page：1 Pages

Low Skew, 1-to-4, Differential-to-HSTL Fantout Buffer

Features • Four differential HSTL compatible outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, C

PWM/PFM Step-down DC-DC Controller

文件：525.56 Kbytes Page：5 Pages

OPERATION INSTRUCTION

文件：1.97588 Mbytes Page：17 Pages