Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip

FEATURES • Sixteen Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias ne

Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

文件：181.32 Kbytes Page：18 Pages

Heyco-Flex™ Quick Twist Conduit Fittings

文件：136.68 Kbytes Page：1 Pages

T1/E1 Interface Modules

文件：176.78 Kbytes Page：1 Pages

Low Skew, 1-to-16 Differential-to- LVDS, Clock Distribution Chip

FEATURES • Sixteen Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias ne

Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

文件：181.32 Kbytes Page：18 Pages

Low Skew, 1-to-16 Differential-to-LVDS, Clock Distribution Chip

文件：181.32 Kbytes Page：18 Pages