Low Skew, 1-to-8, Differential-to-0.7V HCSL Clock Distribution Chip

Features • Eight 0.7V differential HCSL clock output pairs • CLK/nCLK input pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Additive phase jitter, RMS: 0.09ps (typical) • Output skew: 80ps (maximum) • Part-to-par

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：IC CLK BUFFER 1:8 500MHZ 24TSSOP 集成电路（IC） 时钟缓冲器，驱动器

Low Skew, 1-to-8, Differential-to-0.7V HCSL Clock Distribution Chip

文件：528.79 Kbytes Page：16 Pages

Low Skew, 1-to-8, Differential-to-0.7V HCSL Clock Distribution Chip

Features • Eight 0.7V differential HCSL clock output pairs • CLK/nCLK input pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Additive phase jitter, RMS: 0.09ps (typical) • Output skew: 80ps (maximum) • Part-to-par

Low Skew, 1-to-8, Differential-to-0.7V HCSL Clock Distribution Chip

文件：528.79 Kbytes Page：16 Pages

Low Skew, 1-to-8, Differential-to-0.7V HCSL Clock Distribution Chip

Features • Eight 0.7V differential HCSL clock output pairs • CLK/nCLK input pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Additive phase jitter, RMS: 0.09ps (typical) • Output skew: 80ps (maximum) • Part-to-par

Low Skew, 1-to-8, Differential-to-0.7V HCSL Clock Distribution Chip

文件：528.79 Kbytes Page：16 Pages