Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes Page：10 Pages

低压八路透明锁存器（带3态输出）

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

General Description The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes Page：10 Pages

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes Page：10 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC LATCH TRANSP OCT 3ST 20TSSOP 集成电路（IC） 锁存器

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes Page：10 Pages

封装/外壳：20-SOIC（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC LATCH TRANSP OCT 3ST 20SOP 集成电路（IC） 锁存器

Low Voltage Octal Transparent Latch with 3-STATE Outputs

文件：316.77 Kbytes Page：10 Pages