Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary

General Description The LVTH16500 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clo

Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family UBT  Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family UBT  Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family UBT  Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation

Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary

General Description The LVTH16500 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clo

Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary

General Description The LVTH16500 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clo

封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC UNIV BUS TXRX 18BIT 56SSOP 集成电路（IC） 通用总线功能

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments. ‘Widebus ™ Family UBT ™ Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode ‘Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V Vcc) Support Unregulated Battery Ope

3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：135.52 Kbytes Page：9 Pages