9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

1. General description The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold tim

封装/外壳：24-VFQFN 裸露焊盘 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 9BIT 24DHVQFN 集成电路（IC） 触发器

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

文件：239.85 Kbytes Page：16 Pages

封装/外壳：24-VFQFN 裸露焊盘 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 9BIT 24DHVQFN 集成电路（IC） 触发器

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

1. General description The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold tim

9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State

DESCRIPTION The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDE

9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State

DESCRIPTION The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDE

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

1. General description The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold tim