Triple buffer

TRIPLE BUFFER GATE

Features  Wide Supply Voltage Range from 1.65V to 5.5V  ±24mA Output Drive at 3.3V  CMOS Low Power Consumption  IOFF Supports Partial-Power-Down Mode Operation  Inputs Accept up to 5.5V  ESD Protection Tested per JESD 22 Exceeds 2,000V Human Body Model (A114) Exceeds 1,000V Charged D

Triple buffer

1. General description The 74LVC3G34 is a triple buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise a

Triple buffer gate

General description The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5

Triple buffer

Triple buffer

封装/外壳：8-XFDFN 包装：管件 描述：IC BUFFER NON-INVERT 5.5V 8XSON 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：8-XFDFN 包装：卷带（TR） 描述：IC BUFFER NON-INVERT 5.5V 8XSON 集成电路（IC） 缓冲器，驱动器，接收器，收发器