74LVC1G80价格

参考价格:¥0.9168

型号:74LVC1G80GM,115 品牌:NXP 备注:这里有74LVC1G80多少钱,2026年最近7天走势,今日出价,今日竞价,74LVC1G80批发/采购报价,74LVC1G80行情走势销售排行榜,74LVC1G80报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74LVC1G80

Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. F

PANASONIC

松下

74LVC1G80

Single D-type flip-flop; positive-edge trigger

ETC

知名厂家

74LVC1G80

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

NEXPERIA

安世

74LVC1G80

Single D-type flip-flop; positive-edge trigger

PANASONIC

松下

Single D-type flip-flop; positive-edge trigger

ETC

知名厂家

Single D-type flip-flop; positive-edge trigger

ETC

知名厂家

Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. F

PANASONIC

松下

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

ETC

知名厂家

Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. F

PANASONIC

松下

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

ETC

知名厂家

Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. F

PANASONIC

松下

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be drive

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

PANASONIC

松下

Single D-type flip-flop; positive-edge trigger

NEXPERIA

安世

封装/外壳:6-XFDFN 功能:标准 包装:管件 描述:IC FF D-TYPE SNGL 1BIT 6XSON 集成电路(IC) 触发器

ETC

知名厂家

封装/外壳:6-XFDFN 功能:标准 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC FF D-TYPE SNGL 1BIT 6XSON 集成电路(IC) 触发器

ETC

知名厂家

Single D-type flip-flop; positive-edge trigger

文件:796 Kbytes Page:15 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

文件:796 Kbytes Page:15 Pages

NEXPERIA

安世

Single D-type flip-flop; positive-edge trigger

文件:796 Kbytes Page:15 Pages

NEXPERIA

安世

74LVC1G80产品属性

  • 类型

    描述

  • 型号

    74LVC1G80

  • 制造商

    PHILIPS

  • 制造商全称

    NXP Semiconductors

  • 功能描述

    Single D-type flip-flop; positive-edge trigger

更新时间:2026-1-30 10:14:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
恩XP
2038+
SOT-353
8000
原装正品假一罚十
24+
N/A
73000
一级代理-主营优势-实惠价格-不悔选择
恩XP
25+
XSON6
30000
代理全新原装现货,价格优势
恩XP
15
SOP
25123
一级代理,专注军工、汽车、医疗、工业、新能源、电力
Nexperia USA Inc.
24+
6-XFDFN
56300
一级代理/放心采购
TI
20+
XSON6
9850
进口原装公司现货特价
恩XP
2023+
XSON6
30000
十五年行业诚信经营,专注全新正品
NEXPERIA/安世
2450+
NA
9850
只做原厂原装正品现货或订货假一赔十!
恩XP
25+
N/A
21000
原装正品现货,原厂订货,可支持含税原型号开票。
恩XP
24+
标准封装
14548
全新原装正品/价格优惠/质量保障

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