Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow

Quad 2-input NAND gate Rev. 7 ??25 April 2012

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封装/外壳：14-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC GATE NAND 4CH 2-INP 14SSOP 集成电路（IC） 门和反相器

封装/外壳：14-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC GATE NAND 4CH 2-INP 14SSOP 集成电路（IC） 门和反相器

Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow

LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE HIGH PERFORMANCE

DESCRIPTION The 74LVC00A is a low voltage CMOS QUAD 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 4.3ns

Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad 2-Input NAND Gate With 5 V−Tolerant Inputs The 74LVC00A is a high performance, quad 2−input NAND gate operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer imp

QUADRUPLE 2-INPUT NAND GATES

Description The 74LVC00A provides four independent 2-input NAND gates. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power d

Quad 2-input NAND gate

1. General description The 74LVC00A is a quad 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inpu