Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow

Quad 2-input NAND gate

1. General description The 74LVC00A is a quad 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower inpu

Quad 2-input NAND gate

The 74LVC00A provides four 2-input NAND gates.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V appl • 5 V tolerant inputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V)\n• JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n• E;

Quad 2-input NAND gate Rev. 7 ??25 April 2012

文件：197.76 Kbytes Page：14 Pages

Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow

Quad 2-input NAND gate

The 74LVC00A provides four 2-input NAND gates.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V appl • 5 V tolerant inputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V)\n• JESD8-C/JESD36 (2.7 V to 3.6 V)\n\n• E;

Quad 2-input NAND gate

The 74LVC00A-Q100 provides four 2-input NAND gates.\n Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• 5 V tolerant inputs for interfacing with 5 V logic\n• Wide supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL lev;

Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad 2-Input NAND Gate With 5 V−Tolerant Inputs The 74LVC00A is a high performance, quad 2−input NAND gate operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer imp

Low-Voltage CMOS Quad 2-Input NAND Gate

Low-Voltage CMOS Quad 2-Input NAND Gate With 5 V−Tolerant Inputs The 74LVC00A is a high performance, quad 2−input NAND gate operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer imp

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE NAND 4CH 2-INP 14SO 集成电路（IC） 门和反相器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC GATE NAND SCHMIT 4CH 2IN 14SO 集成电路（IC） 门和反相器

Quad 2-input NAND gate Rev. 7 ??25 April 2012

文件：197.76 Kbytes Page：14 Pages

Quad 2-input NAND gate

文件：745.64 Kbytes Page：14 Pages

Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow

Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow

Quad 2-input NAND gate

DESCRIPTION The 74LVC00A is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low pow