Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

General Description The LCX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX125 is fabricated with an advanced CMOS technology to achieve high speed operation while maintai

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUF NON-INVERT 3.6V 14TSSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Low-voltage CMOS quad bus buffer (3-state) with 5 V tolerant inputs and outputs

Features ■ 5 V tolerant inputs and outputs ■ High speed – tPD = 5.2 ns (max.) at VCC = 3 V ■ Power-down protection on inputs and outputs ■ Symmetrical output impedance – |IOH| = IOL = 24 mA (min.) at VCC = 3 V ■ PCI bus levels guaranteed at 24 mA ■ Balanced propagation delay – tPLH ≅ tPHL

Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

General Description The LCX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX125 is fabricated with an advanced CMOS technology to achieve high speed operation while maintai

LOW VOLTAGE CMOS QUAD BUS BUFFER (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS

DESCRIPTION The 74LCX125 is a low voltage CMOS QUAD BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. ■ 5V TOLERANT INPUTS AND OUTPUTS ■ HIGH SPEED : tPD = 5.2 ns (MAX.) at VCC = 3V ■ POWER DOWN PROTECTION ON INPUTS AND OUTPUTS ■

Low voltage CMOS quad bus buffer (3-State) with 5V tolerant inputs and outputs

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Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

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Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs

General Description The LCX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX125 is fabricated with an advanced CMOS technology to achieve high speed operation while maintai