74HCT27价格
参考价格：￥0.6004
型号：74HCT273D,652 品牌：NXP 备注：这里有74HCT27多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT27批发/采购报价，74HCT27行情走势销售排行榜，74HCT27报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT27 | Triple 3-input NOR gate GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor | PHILIPS 飞利浦 |   | |
74HCT27 | Triple 3-input NOR gate | ETC 知名厂家 | ETC | |
74HCT27 | Triple 3-input NOR gate 文件：241.89 Kbytes Page：12 Pages | NEXPERIA 安世 | | |
Octal D-type flip-flop with reset; positive-edge trigger General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D‑type flip‑flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW‑to‑HIGH clock (CP) transition • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Input levels:• For 74HC273-Q100: CMOS level\n• For 74HCT273-Q100: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• C; | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A L • Input levels:• For 74HC273: CMOS level\n• For 74HCT273: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package; | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with reset; positive-edge trigger General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with reset; positive-edge trigger The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A L • Input levels:• For 74HC273: CMOS level\n• For 74HCT273: TTL level\n\n• Common clock and master reset\n• Eight positive edge-triggered D-type flip-flops\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package; | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with reset; positive-edge trigger General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c | PHILIPS 飞利浦 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the | NEXPERIA 安世 | | ||
Triple 3-input NOR gate | ETC 知名厂家 | ETC | | |
Triple 3-input NOR gate 1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa | NEXPERIA 安世 | | ||
Triple 3-input NOR gate | ETC 知名厂家 | ETC | | |
Triple 3-input NOR gate GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor | PHILIPS 飞利浦 | | ||
Triple 3-input NOR gate | ETC 知名厂家 | ETC | | |
Triple 3-input NOR gate 1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa | NEXPERIA 安世 | | ||
Triple 3-input NOR gate | ETC 知名厂家 | ETC | | |
Triple 3-input NOR gate GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor | PHILIPS 飞利浦 | | ||
Triple 3-input NOR gate | ETC 知名厂家 | ETC | | |
Triple 3-input NOR gate 1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa | NEXPERIA 安世 | | ||
Triple 3-input NOR gate 1. General description The 74HC27-Q100; 74HCT27-Q100 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standa | NEXPERIA 安世 | | ||
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
封装/外壳：20-VFQFN 裸露焊盘 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Octal D-type flip-flop with reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Triple 3-input NOR gate 文件：241.89 Kbytes Page：12 Pages | NEXPERIA 安世 | | ||
Triple 3-input NOR gate 文件：703.84 Kbytes Page：15 Pages | NEXPERIA 安世 | | ||
Triple 3-input NOR gate 文件：241.89 Kbytes Page：12 Pages | NEXPERIA 安世 | | ||
Triple 3-input NOR gate 文件：703.84 Kbytes Page：15 Pages | NEXPERIA 安世 | | ||
Triple 3-input NOR gate 文件：241.89 Kbytes Page：12 Pages | NEXPERIA 安世 | | ||
Triple 3-input NOR gate 文件：703.84 Kbytes Page：15 Pages | NEXPERIA 安世 | | ||
TRIPLE 3-INPUT NOR GATE DESCRIPTION The M54/74HCT27 is a high speed CMOS TRIPLE 3-INPUT NOR GATE fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 9 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) ■ OUTPUT DRI | STMICROELECTRONICS 意法半导体 | | ||
TRIPLE 3-INPUT NOR GATE DESCRIPTION The M54/74HCT27 is a high speed CMOS TRIPLE 3-INPUT NOR GATE fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 9 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) ■ OUTPUT DRI | STMICROELECTRONICS 意法半导体 | | ||
TRIPLE 3-INPUT NOR GATE DESCRIPTION The M54/74HCT27 is a high speed CMOS TRIPLE 3-INPUT NOR GATE fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 9 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) ■ OUTPUT DRI | STMICROELECTRONICS 意法半导体 | | ||
High Speed CMOS Logic Triple 3-Input NOR Gate 文件：43.78 Kbytes Page：7 Pages | TI 德州仪器 | |
74HCT27产品属性
- 类型
描述
- VCC (V)：
4.5 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 4
- tpd (ns)：
15
- fmax (MHz)：
36
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
78
- Ψth(j-top) (K/W)：
9.4
- Rth(j-c) (K/W)：
50
- Package name：
DHVQFN20
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
恩XP |
24+ |
标准封装 |
22238 |
全新原装正品/价格优惠/质量保障 |
|||
恩XP |
2016+ |
SOP |
4000 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
NEXPERIA/安世 |
25+ |
SOT360-1 |
600000 |
NEXPERIA/安世全新特价74HCT273PW-Q100J即刻询购立享优惠#长期有排单订 |
|||
NEXPERIA/安世 |
21+ |
TSSOP |
8080 |
只做原装,质量保证 |
|||
NEXPERIA/安世 |
24+ |
TSSOP |
11000 |
只做原装真实库存13714450367 |
|||
恩XP |
2025+ |
N/A |
70000 |
柒号只做原装 现货价秒杀全网 |
|||
PHI |
24+ |
SOP |
125 |
原装优势现货 |
|||
恩XP |
25+ |
N/A |
18798 |
原装正品现货,原厂订货,可支持含税原型号开票。 |
|||
NEXPERIA/安世 |
23+ |
NA |
9990 |
只有原装 |
|||
NEXPERIA/安世 |
2025+ |
TSSOP |
5000 |
原装进口价格优 请找坤融电子! |
74HCT27规格书下载地址
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2019-12-28
DdatasheetPDF页码索引
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