74HCT112价格
参考价格：￥1.2170
型号：74HCT112D,652 品牌：NXP 备注：这里有74HCT112多少钱，2026年最近7天走势，今日出价，今日竞价，74HCT112批发/采购报价，74HCT112行情走势销售排行榜，74HCT112报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HCT112 | Dual JK flip-flop with set and reset; negative-edge trigger 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen | NEXPERIA 安世 |   | |
74HCT112 | Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip | PHILIPS 飞利浦 | | |
Dual JK flip-flop with set and reset; negative-edge trigger 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip | PHILIPS 飞利浦 | | ||
74HCT112DB - dual JK flip-flop with set and reset; negative-edge trigger dual JK flip-flop with set and reset; negative-edge trigger - The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous act ·Input levels:·For 74HC112: CMOS level\n·For 74HCT112: TTL level; | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; negative-edge trigger The 74HC112-Q100; 74HCT112-Q100 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the cloc | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with set and reset; negative-edge trigger GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with set and reset; negative-edge trigger 1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen | NEXPERIA 安世 | | ||
Dual JK flip-flop with set and reset; negative-edge trigger The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. T • Input levels:• For 74HC112: CMOS level\n• For 74HCT112: TTL level\n\n• Asynchronous set and reset\n• Specified in compliance with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +8; | NEXPERIA 安世 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 16SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SSOP 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger 文件：55.1 Kbytes Page：8 Pages | TI 德州仪器 | |
74HCT112产品属性
- 类型
描述
- VCC (V)：
4.5 - 5.5
- Logic switching levels：
TTL
- Output drive capability (mA)：
± 4
- tpd (ns)：
19
- fmax (MHz)：
70
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
75
- Ψth(j-top) (K/W)：
1.7
- Rth(j-c) (K/W)：
33
- Package name：
SO16
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Nexperia |
25+ |
N/A |
22360 |
样件支持,可原厂排单订货! |
|||
Nexperia(安世) |
25+ |
TSSOP16 |
3238 |
原装现货,免费供样,技术支持,原厂对接 |
|||
HAR |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
PHI |
2026+ |
DIP-16 |
65428 |
百分百原装现货 实单必成 |
|||
PHIL |
24+/25+ |
25 |
原装正品现货库存价优 |
||||
恩XP |
2223+ |
SOP16 |
26800 |
只做原装正品假一赔十为客户做到零风险 |
|||
恩XP |
23+ |
NA |
4326 |
专做原装正品,假一罚百! |
|||
PHI |
DIP16 |
275000 |
一级代理原装正品,价格优势,长期供应! |
||||
74HCT112N |
25+ |
2 |
2 |
||||
恩XP |
18+ |
SOP16 |
85600 |
保证进口原装可开17%增值税发票 |
74HCT112规格书下载地址
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DdatasheetPDF页码索引
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