型号 功能描述 生产厂家 企业 LOGO 操作

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

更新时间:2025-12-26 23:01:01
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
XINBOLE/芯伯乐
24+
NA/
13352
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恩XP
24+
标准封装
46248
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STC
23+
SOP-14
20000
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MOT
24+
SOP20
20000
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NEXPERIA/安世
25+
SOT402-1
600000
NEXPERIA/安世全新特价74HC73PW即刻询购立享优惠#长期有排单订
MOT
23+
SOP3.99
3200
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PHI
25+
SOP3.9
2987
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MOTOROLA
DIP
6500
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NEXPERIA/安世
2025+
SOP
5000
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PHI
02+/03+
NULL
2242
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