8-bit shift register with input flip-flops

GENERAL DESCRIPTION The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 8-bit parallel storage register inputs • Shift register has direct overriding lo

8-bit shift register with input flip-flops

1. General description The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift registe

8-bit shift register with input flip-flops

The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from • Complies with JEDEC standard JESD7A\n• Input levels:• For 74HC597: CMOS level\n• For 74HCT597: TTL level\n\n• 8-bit parallel storage register inputs\n• Shift register has direct overriding load and clear\n• ESD protection:• HBM EIA/JESD22-A114F exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\;

8-bit shift register with input flip-flops

The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from • Complies with JEDEC standard JESD7A\n• Input levels:• For 74HC597: CMOS level\n• For 74HCT597: TTL level\n\n• 8-bit parallel storage register inputs\n• Shift register has direct overriding load and clear\n• ESD protection:• HBM EIA/JESD22-A114F exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\;

8-bit shift register with input flip-flops

The 74HC597-Q100; 74HCT597-Q100 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C\n\n• Complies with JEDEC standard JESD7A\n• Input levels:• For 74HC597-Q100: CMOS level\n• For 74HCT597-Q100: TTL level\n\n• 8-bit parallel storage register inputs\n• ;

8-bit shift register with input flip-flops

1. General description The 74HC597-Q100; 74HCT597-Q100 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shi

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：并行至串行 包装：管件 描述：IC SHIFT REGISTER 8BIT 16SOIC 集成电路（IC） 移位寄存器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：并行至串行 包装：管件 描述：IC SHIFT REGISTER 8BIT 16SOIC 集成电路（IC） 移位寄存器

8-bit shift register with input flip-flops

文件：781.74 Kbytes Page：20 Pages

8-bit shift register with input flip-flops

GENERAL DESCRIPTION The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 8-bit parallel storage register inputs • Shift register has direct overriding lo

8-bit shift register with input flip-flops

GENERAL DESCRIPTION The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 8-bit parallel storage register inputs • Shift register has direct overriding lo

8 BIT LATCH/SHIFT REGISTER

DESCRIPTION The M54/74HC597 is a high speed CMOS 8-BIT LATCH/SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED fMAX = 60 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATIO

High Speed CMOS Logic 8-Bit Shift Register with Input Storage

文件：48.79 Kbytes Page：10 Pages