8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

1. General description The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is de

8-bit synchronous binary down counter

GENERAL DESCRIPTION\nThe 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.\nThe 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which is ac • Cascadable\n• Synchronous or asynchronous preset\n• Output capability: standard\n• ICC category: MSI ;

8-bit synchronous binary down counter

The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on eac • Cascadable\n• Synchronous or asynchronous preset\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• CMOS input levels\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +80 °C and from -40 ;

8-bit synchronous binary down counter

1. General description The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is de

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is decremented by one count on eac • Cascadable\n• Synchronous or asynchronous preset\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• CMOS input levels\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +80 °C and from -40 ;

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which

8-bit synchronous binary down counter

1. General description The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. In normal operation, the counter is de

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC 8BIT SYNC BINARY DOWN 16SOIC 集成电路（IC） 计数器，除法器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC 8BIT SYNC BINARY DOWN 16-SSOP 集成电路（IC） 计数器，除法器

8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：300.93 Kbytes Page：14 Pages