Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

DUAL DECADE RIPPLE COUNTER

DUAL DECADE RIPPLE COUNTER

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

1. General description The 74HC393; 74HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on

DUAL 4-BIT BINARY RIPPLE COUNTER

Dual 4-bit binary ripple counter

High Speed CMOS Logic

Features Low Input Current: 1μA Output Drive Capability: 10 LSTTL loads Outputs Directly Interface to CMOS, NMOS, & TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS393

High Speed CMOS Logic

Features Low Input Current: 1μA Output Drive Capability: 10 LSTTL loads Outputs Directly Interface to CMOS, NMOS, & TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS393

Dual 4-bit binary ripple counter

Dual 4-bit binary ripple counter

1. General description The 74HC393; 74HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on

Dual 4-bit binary ripple counter

1. General description The 74HC393-Q100; 74HCT393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP.

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

1. General description The 74HC393; 74HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on

Dual 4-bit binary ripple counter

CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Dual Binary Counter General The 74HC393D is a high speed CMOS 4-BIT BINARY COUNTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It contains two indepe

EVALUATION FIXTURE

FEATURES * STAND-ALONE CAPABILITY * FLEXIBLE CLOCK PROGRAMMING * USER-CONFIGURABLE A/D CONVERTER OPERATION * ANALOG BREADBOARD AREA * DIGITAL BREADBOARD AREA * FLEXIBLE REFERENCE VOLTAGE PROGRAMMING APPLICATIONS * DATA ACQUISTION * PERSONAL DIGITAL ASSISTANTS * 4- OR 5-WIRE RESISTIVE

Dual 4-bit binary ripple counter

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

1. General description The 74HC393-Q100; 74HCT393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP.

Dual 4-bit binary ripple counter

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

1. General description The 74HC393; 74HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on

Dual 4-bit binary ripple counter

Dual 4-bit binary ripple counter

1. General description The 74HC393-Q100; 74HCT393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP.

Dual 4-bit binary ripple counter

1. General description The 74HC393-Q100; 74HCT393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP.

High?밣erformance Silicon?밎ate CMOS

文件：268.46 Kbytes Page：9 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DUAL DEC RIPPLE COUNT 16SOIC 集成电路（IC） 计数器，除法器

BCD / Decade counters

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC DUAL DECADE RIPP COUNT 16SSOP 集成电路（IC） 计数器，除法器

Dual decade ripple counter

High Speed CMOS Logic

文件：456.32 Kbytes Page：6 Pages

Dual 4-bit binary ripple counter

Dual 4-bit binary ripple counter

文件：734.87 Kbytes Page：20 Pages

Dual 4-bit binary ripple counter

文件：734.87 Kbytes Page：20 Pages

Dual 4-bit binary ripple counter

文件：734.87 Kbytes Page：20 Pages

Dual 4-bit binary ripple counter

文件：734.87 Kbytes Page：20 Pages