3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

3-to-8 line decoder, demultiplexer with address latches; inverting

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A.\n The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentiall • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM EIA/JESD22-A114-B exceeds 2000 V\n• MM EIA/JESD22-A115-A exc;

3-to-8 line decoder, demultiplexer with address latches inverting

文件：107.6 Kbytes Page：19 Pages

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：托盘 描述：IC DECODER/DEMUX 1X3:8 16SSOP 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：托盘 描述：IC DECODER/DEMUX 1X3:8 16SSOP 集成电路（IC） 信号开关，多路复用器，解码器

3-to-8 line decoder/demultiplexer with address latches; inverting

GENERAL DESCRIPTION The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or ind

3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.099 Kbytes Page：10 Pages

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.099 Kbytes Page：10 Pages

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：381.06 Kbytes Page：16 Pages