丝印代码：74HC123D；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Dual Monostable Multivibrator General The 74HC123D is a high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. There a

丝印代码：74HC125D；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Quad Bus Buffer, Non-Inverted 3-State Outputs 74HC125D: Quad Bus Buffer 74HC126D: Quad Bus Buffer General The 74HC125D,74HC126D are high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equiv

丝印代码：74HC126D；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Quad Bus Buffer, Non-Inverted 3-State Outputs 74HC125D: Quad Bus Buffer 74HC126D: Quad Bus Buffer General The 74HC125D,74HC126D are high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equiv

丝印代码：74HC126；Quad bus buffer (3-state)

Features • High-speed: tPD = 8 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIL = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 6 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating vo

丝印代码：74HC126Y；Quad bus buffer (3-state)

Features • High-speed: tPD = 8 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIL = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 6 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating vo

High Speed CMOS Logic

Features Triggerable via positive or negative edge Re-triggerable for very long pulses up to 100% duty factor Direct reset terminates output Schmitt trigger action for A & B inputs Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and

Dual retriggerable monostable multivibrator with reset

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123; 74HCT123 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the edge trig

High Speed CMOS Logic

Features Triggerable via positive or negative edge Re-triggerable for very long pulses up to 100% duty factor Direct reset terminates output Schmitt trigger action for A & B inputs Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and

Dual retriggerable monostable multivibrator with reset

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123; 74HCT123 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the edge trig

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123-Q100; 74HCT123-Q100 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the

Dual retriggerable monostable multivibrator with reset

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123; 74HCT123 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the edge trig

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123-Q100; 74HCT123-Q100 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the

Dual retriggerable monostable multivibrator with reset

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123; 74HCT123 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the edge trig

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123-Q100; 74HCT123-Q100 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123-Q100; 74HCT123-Q100 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the

QUAD BUS BUFFERS (3-STATE)

DESCRIPTION The M54/74HC125/126 are high speed CMOS QUAD BUS BUFFER (3-STATE) FABRICATED IN SILICON GATE C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices require the same 3-STATE control input G to be taken hig

Quad buffer/line driver; 3-state

1. General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to

High Speed CMOS Logic

Features Output Drive Capability: 15 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V Function compatible with 74LS125 High Noise Immunity CMOS process.

Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

1. General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

Quad buffer/line driver; 3-state

1. General description The 74HC125-Q100; 74HCT125-Q100 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes which enable the use of current limiting resi

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

Quad buffer/line driver; 3-state

1. General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to

Quad buffer/line driver; 3-state

1. General description The 74HC125-Q100; 74HCT125-Q100 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes which enable the use of current limiting resi

Quad buffer/line driver; 3-state

1. General description The 74HC125-Q100; 74HCT125-Q100 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes which enable the use of current limiting resi

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of