Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

J-K Type Flip-Flops

dual JK flip-flop with set and reset; negative-edge trigger - The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous act ·Input levels:·For 74HC112: CMOS level\n·For 74HCT112: TTL level;

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 16SSOP 集成电路（IC） 触发器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 16SSOP 集成电路（IC） 触发器

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs ar