16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is

16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：68.99 Kbytes Page：6 Pages

16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：181.05 Kbytes Page：10 Pages

封装/外壳：24-DIP（0.300"，7.62mm） 功能：并行或串行至串行 包装：管件 描述：IC SHIFT REGISTER SER/PAR 24DIP 集成电路（IC） 移位寄存器

16-bit serial/parallel-in, serial-out shift register 3-State

DESCRIPTION The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the mode (M) input is High, information present on the parallel data (D0–D15) inputs is entered on the falling edge of the clock pulse (CP) input signal. When M is Low,

16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is

16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：68.99 Kbytes Page：6 Pages

54F676 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：431.12 Kbytes Page：12 Pages

16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is