Octal Registered Transceiver with Parity and Flags

General Description The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output wi

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC TXRX NON-INVERT 5.5V 28PLCC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal Registered Transceiver with Parity and Flags

General Description The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output wi

Octal registered transceiver with parity and flags 3-State

DESCRIPTION The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag flip-flop that is set automatically as the register is lo

Octal Registered Transceiver with Parity and Flags

General Description The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output wi

Octal registered transceiver with parity and flags 3-State

DESCRIPTION The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag flip-flop that is set automatically as the register is lo