丝印：pT；Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition

Low-power dual D-type flip-flop; positive-edge trigger

封装/外壳：8-XFDFN 功能：标准 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 8XSON 集成电路（IC） 触发器

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition

Low-power dual D-type flip-flop; positive-edge trigger

文件：94.62 Kbytes Page：18 Pages

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger

Low-power dual D-type flip-flop; positive-edge trigger

文件：94.62 Kbytes Page：18 Pages