封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE DUAL 9BIT 56TSSOP 集成电路（IC） 触发器

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

1. General description The 74ALVT16823 is an 18-bit positive-edge triggered D-type flip-flop with 3-state outputs, reset and enable. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

1. General description The 74ALVT16823 is an 18-bit positive-edge triggered D-type flip-flop with 3-state outputs, reset and enable. The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge