18-bit bus-interface D-type flip-flop with reset and enable with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positiv

18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state

1 General description The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers w

18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state

1 General description The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers w

18-bit bus-interface D-type flip-flop with reset and enable with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positiv

18-bit bus-interface D-type flip-flop with reset and enable with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positiv