20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

74ALVCH16821DL - 20-bit bus-interface D-type flip-flop' positive-edge trigger (3-State)

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

1 General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered

封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE DUAL 10BIT 56SSOP 集成电路（IC） 触发器

封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE DUAL 10BIT 56SSOP 集成电路（IC） 触发器

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：312.07 Kbytes Page：12 Pages

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件：312.07 Kbytes Page：12 Pages

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

1 General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered