型号 功能描述 生产厂家&企业 LOGO 操作
74ALVCH16821DL

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

Philips

飞利浦

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

Philips

飞利浦

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

1 General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

封装/外壳:56-BSSOP(0.295",7.50mm 宽) 功能:标准 包装:管件 描述:IC FF D-TYPE DUAL 10BIT 56SSOP 集成电路(IC) 触发器

ETC

知名厂家

封装/外壳:56-BSSOP(0.295",7.50mm 宽) 功能:标准 包装:管件 描述:IC FF D-TYPE DUAL 10BIT 56SSOP 集成电路(IC) 触发器

ETC

知名厂家

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件:312.07 Kbytes Page:12 Pages

TI

德州仪器

3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

文件:312.07 Kbytes Page:12 Pages

TI

德州仪器

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. FEATURES • Wide supply voltage range of

Philips

飞利浦

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

1 General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

74ALVCH16821DL产品属性

  • 类型

    描述

  • 型号

    74ALVCH16821DL

  • 功能描述

    触发器 20-BIT BUS INTERFACE

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2025-8-14 18:05:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
PHI
21+
SSOP
2000
10年芯程,只做原装正品现货,欢迎加微信垂询!
RENESAS(瑞萨)/IDT
24+
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
PHI
21+
SSOP
2000
原装现货假一赔十
PHI
25+
TSSOP56
21
⊙⊙新加坡大量现货库存,深圳常备现货!欢迎查询!⊙
Nexperia
25+
电联咨询
7800
公司现货,提供拆样技术支持
恩XP
25+
TSSOP56
4500
全新原装、诚信经营、公司现货销售
PHI
2450+
SSOP
8850
只做原装正品假一赔十为客户做到零风险!!
TI
24+
120
PHI
23+
SSOP
3000
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
IDT
TSSOP
86
正品原装--自家现货-实单可谈

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