18-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74ALVC16834A is an 18-bit registered driver. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through stan

18-bit registered driver with inverted register enable; 3-state

1 General description The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is l

18-bit registered driver with inverted register enable; 3-state

1 General description The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is l

18-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74ALVC16834A is an 18-bit registered driver. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through stan

18-bit registered driver with inverted register enable (3‑state)

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC BUF NON-INVERT 3.6V 56TSSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC BUF NON-INVERT 3.6V 56TSSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable

Description The HD74ALVC16834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Features • Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” • Typical VOL ground bounce 2.0 V (@VCC = 3.3 V