Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26??Series Resistors in Outputs

General Description The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications suc

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs

18-bit registered driver with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tran

18-bit registered driver with 30 Ω termination resistors; 3-state

1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW

18-bit registered driver with 30 Ω termination resistors; 3-state

1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW

18-bit registered driver with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tran

18-bit registered driver with 30 Ohm termination resistors; 3-state

The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).\n When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of C • Wide supply voltage range of 1.2 V to 3.6 V\n• Complies with JEDEC standard no. 8-1A\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Current drive ±12 mA at 3.0 V\n• MULTIBYTETM flow-through standard pin-out architecture\n• Low inductance multiple VCC and GND pins for minimum ;

丝印代码：ALVC162835；18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 2 ns at 3.3 V ±12-mA Output Drive at 3.3 V Ideal for Use in PC100 Register DIMM, Revision 1.1 Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Required Latch-U

丝印代码：ALVC162835；18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 2 ns at 3.3 V ±12-mA Output Drive at 3.3 V Ideal for Use in PC100 Register DIMM, Revision 1.1 Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Required Latch-U

丝印代码：ALVC162835；18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 V to 3.6 V · Max tpd of 2 ns at 3.3 V · ±12-mA Output Drive at 3.3 V · Ideal for Use in PC100 Register DIMM, Revision 1.1 · Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Requi

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 V to 3.6 V · Max tpd of 2 ns at 3.3 V · ±12-mA Output Drive at 3.3 V · Ideal for Use in PC100 Register DIMM, Revision 1.1 · Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Requi

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26??Series Resistors in Outputs

General Description The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications suc

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs

General Description\nThe ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications such ■ Compatible with PC100 DIMM module specifications\n■ 1.65V to 3.6V VCC specifications provided\n■ 3.6V tolerant inputs and outputs\n■ 26Ω series resistors in outputs\n■ tPD (CLK to On)\n   5.4 ns max for 3.0V to 3.6V VCC\n   6.3 ns max for 2.3V to 2.7V VCC\n   9.2 ns max for 1.65V to 1.95V VCC\n■ P;

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC UNIV BUS DVR 18BIT 56TSSOP 集成电路（IC） 通用总线功能

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

文件：212.64 Kbytes Page：12 Pages

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

文件：212.64 Kbytes Page：12 Pages

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

文件：212.64 Kbytes Page：12 Pages

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

文件：212.64 Kbytes Page：12 Pages

封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 包装：管件 描述：IC UNIV BUS DVR 18BIT 56SSOP 集成电路（IC） 通用总线功能

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

文件：190.61 Kbytes Page：11 Pages

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

文件：190.61 Kbytes Page：11 Pages

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

文件：190.61 Kbytes Page：11 Pages