Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

Triple 3-Input NAND gate

Triple 3-Input NAND gate

Triple 3-Input NAND gate

Triple 3-Input NAND gate

Triple 3-Input NAND gate

Triple 3-Input NAND gate

Hex Inverting Drivers with Open Collector Outputs

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Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL