8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

8-bit serial-in/serial-out or parallel-out shift register

NPN general-purpose double transistors output latches; 3-state

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行，串行 包装：管件 描述：IC 8BIT SHFT REGSTR 3-ST 16SOIC 集成电路（IC） 移位寄存器

8-bit serial-in/serial-out or parallel-out shift register with output latches

8-bit serial-in/serial-out or parallel-out shift register with output latches

文件：794.74 Kbytes Page：22 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行，串行 包装：卷带（TR） 描述：IC SHIFT REG 8BIT SER 16SOIC 集成电路（IC） 移位寄存器

8-bit serial-in/serial-out or parallel-out shift register with output latches

1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DESCRIPTION The 74AHC/AHCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The s

8-BIT SHIFT REGISTER 8-BIT OUTPUT REGISTER

文件：255.08 Kbytes Page：10 Pages

NPN general-purpose double transistors output latches; 3-state

NPN general-purpose double transistors output latches; 3-state