Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The c

Octal D-type flip-flop with reset; positive-edge trigger

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs

Octal D-type flip-flop with reset; positive-edge trigger

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.\n The • Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Ideal buffer for MOS microcontroller or memory\n• Common clock and master reset\n• Related product versions:• 74AHC377; 74AHCT377 for clock enable version\n• 74AHC373; 74AHCT373 for ;

Octal D-type flip-flop with reset; positive-edge trigger

The 74AHC273-Q100; 74AHCT273-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC273-Q100; 74AHCT273-Q100 has eight edge-triggered, D-type flip-flops with individual D inputs and • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Ideal buffer for MOS microcontroller or memory;

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

文件：814.17 Kbytes Page：19 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The c

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The c

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The c

OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

文件：584.66 Kbytes Page：18 Pages