DESCRIPTION

The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74AHC/AHCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

FEATURES

• Ideal buffer for MOS microcontroller or memory

• Common clock and master reset

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101 exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt trigger actions

• Inputs accepts voltages higher than VCC

• See ‘377’ for clock enable version

• See ‘373’ for transparent latch version

• See ‘374’ for 3-state version

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Specified from −40 to +85 °C and −40 to +125 °C.