Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) out puts. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF D-TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) out puts. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF D-TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) out puts. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and

Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) out puts. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and