Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

Octal D-type flip-flop with enable

DESCRIPTION The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization appli

Octal D-type flip-flop with enable

DESCRIPTION The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization appli

Octal D-type flip-flop with enable

DESCRIPTION The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization appli

Octal D-type flip-flop with enable

DESCRIPTION The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization appli

Octal D-type flip-flop with enable

DESCRIPTION The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization appli

Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

Octal D-Type Flip-Flop with Clock Enable

General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setu

Octal D-type flip-flop with enable

DESCRIPTION The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization appli

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器