18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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