Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of

Dual JK Fllp-Flop Product Specification

DESCRIPTION The '73 is a dual flip-flop with individual J, K, Clock and direct Reset inputs. The 7473 is positive pulse-triggered. JK infor- mation is loaded into the master while the Clock is HIGH and transferred to the slave on the HIGH-to-LOW transition. For the 7473, the J and K inputs

D-Sub 插座组件：垂直，外壳尺寸 4，2.77mm

外壳尺寸为 4 的 PCB D-Sub AMPLIMITE 插座组件，中心线间距为 2.77mm，采用垂直 PCB 安装方向。用于信号电路应用，工作温度范围为 -55-105℃。

D-Sub 插座组件：垂直，外壳尺寸 5，2.77mm

外壳尺寸为 5 的 PCB D-Sub AMPLIMITE 插座组件，中心线间距为 2.77mm，采用垂直 PCB 安装方向。用于信号电路应用，工作温度范围为 -55-105℃。

D-Sub 插座组件：垂直，外壳尺寸 4，2.77mm

外壳尺寸为 4 的 PCB D-Sub AMPLIMITE 插座组件，中心线间距为 2.77mm，采用垂直 PCB 安装方向。用于信号电路应用，工作温度范围为 -55-105℃。

XFP Cage

Description: Heat Sink for XFP Cage Assembly, 10 Gigabit Small Form Factor Pluggable Compatible, PCI Height, Power Level Up-1.5W Application Module-to-Board

XFP Cage

Description: Heat Sink for XFP Cage Assembly, 10 Gigabit Small Form Factor Pluggable Compatible, PCI Height, Power Level Up-1.5W Application Module-to-Board

包装：盒 描述：CONN D-SUB RCPT 37POS VERT SLDR 连接器，互连器件 D-Sub 连接器组件

包装：托盘 描述：CONN D-SUB RCPT 37POS VERT SLDR 连接器，互连器件 D-Sub 连接器组件

XPAK 10Gbps Guide Rail

文件：228.66 Kbytes Page：2 Pages

X2 10 Gbps System

文件：546.67 Kbytes Page：2 Pages

XFP CAGE. HEAT SINK CLIP

文件：52.23 Kbytes Page：1 Pages

PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION

文件：60.06 Kbytes Page：1 Pages

RoHS Compliant 1-by-1 SFP Cage

文件：266.53 Kbytes Page：2 Pages

RoHS Compliant 1-by-1 SFP Cage

文件：266.53 Kbytes Page：2 Pages

RoHS Compliant 1-by-1 SFP Cage

文件：266.53 Kbytes Page：2 Pages

RoHS Compliant 1-by-1 SFP Cage

文件：266.53 Kbytes Page：2 Pages

RoHS Compliant 1-by-1 SFP Cage

文件：266.53 Kbytes Page：2 Pages

RoHS Compliant 1-by-1 SFP Cage

文件：266.53 Kbytes Page：2 Pages

XPAK 10 Gbps Transceiver

文件：104.2 Kbytes Page：2 Pages

Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of

Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of

QUAD BTL DRIVER WITH VOLTAGE REGULATOR

DESCRIPTION This device is a quad power driver circuit in BTL configuration, intended for use as a power driver for servo systems with a single supply. It’s specially dedicated to compact disc players and it’s capable of driving focus & tracking actuators sledge & spindle motors. The re

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes Page：13 Pages

Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Transistor transistor logic

INTEGRATED CIRCUIT PINOUTS

DUAL J-K FLIP-FLOPS WITH CLEAR

DUAL J-K FLIP-FLOPS WITH CLEAR