Cyclone V Device Overview

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa • FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the

Cyclone V Device Overview

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa • FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the

Cyclone V Device Overview

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa • FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the

Cyclone V Device Datasheet

文件：945.38 Kbytes Page：93 Pages

Cyclone V Device Datasheet

文件：945.38 Kbytes Page：93 Pages

Cyclone® V 5CSXC5 FPGA

封装/外壳：672-FBGA 包装：散装 描述：IC SOC CORTEX-A9 800MHZ 672UBGA 集成电路（IC） 片上系统（SoC）

Cyclone® V 5CSXC5 FPGA

Cyclone V Device Datasheet

文件：945.38 Kbytes Page：93 Pages

Cyclone V Device Datasheet

文件：945.38 Kbytes Page：93 Pages

封装/外壳：672-FBGA 包装：散装 描述：IC SOC CORTEX-A9 600MHZ 672UBGA 集成电路（IC） 片上系统（SoC）

Cyclone® V 5CSXC5 FPGA

Cyclone V Device Datasheet

文件：945.38 Kbytes Page：93 Pages